LC88FC3K0A Datasheet, PDF (4/48 Pages) ON Semiconductor – 16-bit Microcontroller

LC88FC3K0A
 _UART0
<1> Data length : 8 bits (LSB first)
<2> Start bits : 1 bit
<3> Stop bits : 1 bit
<4> Parity bits : None/even parity/odd parity
<5> Transfer rate : 4/8 cycle
<6> Baudrate source clock: P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock
source) or Timer4 cycle.
<7> Full duplex communication
Note : The “cycle” refers to one period of the baudrate clock source.
 _UART2
<1> Data length : 8 bits (LSB first)
<2> Start bits : 1 bit
<3> Stop bits : 1/2 bit
<4> Parity bits : None/even parity/odd parity
<5> Transfer rate : 8 to 4096 cycle
<6> Baudrate source clock: System clock/OSC0/OSC1/P26 input signal
<7> Wakeup function
<8> Full duplex communication
Note : The “cycle” refers to one period of the baudrate clock source.
 _UART3
<1> Data length : 8 bits (LSB first)
<2> Start bits : 1 bit
<3> Stop bits : 1/2 bit
<4> Parity bits : None/even parity/odd parity
<5> Transfer rate : 8 to 4096 cycle
<6> Baudrate source clock: System clock/OSC0/OSC1/P36 input signal
<7> Wakeup function
<8> Full duplex communication
Note : The “cycle” refers to one period of the baudrate clock source.
 AD converter
<1> 12/8 bits resolution selectable
<2> Analog input: 16 channels
<3> Comparator mode
 PWM
 _{PWM0 : Multifrequency 12-bit PWM  2 channels (PWM0A and PWM0B)}
<1> 2-channel pairs controlled independently of one another
<2> Clock source selectable from system clock or OSC1
<3> 8-bit prescaler: TPWMR0= (prescaler value + 1)  clock period
<4> 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit
<5> Fundamental wave PWM mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
<6> Fundamental wave + additional pulse mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
Overall period
High pulse width
: Fundamental wave period  16
: 0 to (Fundamental wave period - TPWMR0)
 CRC operating circuit
 Watchdog timer
<1> Driven by the base timer + internal watchdog timer dedicated counter
<2> Interrupt or reset mode selectable
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