LC88FC3K0A Datasheet, PDF (32/48 Pages) ON Semiconductor – 16-bit Microcontroller

LC88FC3K0A
Parameter
Stop condition
setup time
Data hold time
Data setup time
Symbol
tSU;STO
Applicable
Pin/Remarks
Conditions
SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
VDD [V]
Specification
Min
typ max unit
1.0
Tfilt
tSU;STOx SM1CK (PB4)  Standard clock mode
SM1DA (PB5)
 Specified as interval up to
time when output state starts
2.7 to 3.6
4.9
changing.
 High-speed clock mode
 Specified as interval up to
time when output state starts
1.1
changing.
tHD;DAT SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
0
tHD;DATx SM1CK (PB4)  Specified as interval up to ^{2.7 to 3.6}
SM1DA (PB5) ^{time when output state starts}
changing.
1
tSU;DAT SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
1
tSU;DATx
SM1CK (PB4)  Specified as interval up to
SM1DA (PB5) ^{time when output state starts}
changing.
2.7 to 3.6
1tSCL-1.5Tfilt
tF
SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
2.7 to 3.6
sec
Tfilt
1.5
Tfilt
300
SM0CK and
tF
SM0DA pins fall
time
SM1CK (PB4)  When SMIIC register
SM1DA (PB5) ^{control bits}
PSLW=1, PHV=1
3
20+0.1Cb
(Note 4-10-3)
250
ns
 SM0CK, SM0DA port
output FAST mode
3 to 3.6
100
 Cb ≤ 100pF
Note 4-10-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-10-2 : The value of Tfilt is determined by the values of the register SMIC1BRG, bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
tCYC1
0
1
tCYC2
1
0
tCYC3
1
1
tCYC4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range :
250 ns ≥ Tfilt > 140 ns
Note 4-10-3 : Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF
Note 4-10-4 : The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as
follows :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100 kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC1BRG as follows :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400 kHz
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