AMIS-30622 Datasheet, PDF (33/42 Pages) AMI SEMICONDUCTOR – I2C Microstepping Motordriver

AMIS-30622
9.2.4.3. Physical Address of the circuit
The circuit is provided with a physical address in order to discriminate this circuit from other ones on the I²C bus.
This address is coded on 7 bits (2 bits being internally hardwired to ‘1’), yielding the theoretical possibility of 32
different circuits on the same bus. It is a combination of 4 OTP memory bits (see § 9.2.2.13 OTP Memory
Structure) and of the externally hardwired address bits (pin HW). HW must either be connected to Ground or to
Vbat. When HW is not connected and left floating correct functionality of the positioner is not guaranteed. The
motor will be driven to the programmed Secure Position. (see § 9.2.2.12 Application parameters SecPos [10:0])
AD6
‘1’
AD5
‘1’
AD4
PA3
AD3
PA2
AD2
PA1
AD1
PA0
AD0
HW
Physical address
OTP memory
Hardwired bit (to Gnd or Vbat)
The AMIS-30622 supports a “general call” address. Therefore the circuit is addressable with either the physical
slave address or with address “000 0000”.
9.2.4.4. Write data to AMIS-30622
A complete transmission consists of the followings: a Start condition, the slave address (7-bit), a read/write bit
(‘0’ = write, ‘1’ = read), and an acknowledge bit. Any further databytes are followed by an acknowledge bit. The
acknowledge bit is used to signal a correct reception of the data to the transmitter. In this case the AMIS-30622
pulls the SDA line to ‘0’. The AMIS-30622 reads the incoming data at SDA on every rising edge of the SCK
signal. To finish the transmission the master has to transmit a Stop condition. Some commands for the AMIS-
30622 are supporting 8 bytes of data, other commands are transmitting 2 bytes of data.
S Slave address R/W A
Data
A
Data
AH
‘0’ (write)
Master to slave
Slave to master
N Bytes + acknowledge
S : Start condition
H : Stop condition
A : SDA = ‘0’ ⇔ acknowledge (A)
SDA = ‘1’ ⇔ no acknowledge (Ab)
9.2.4.5. Read data from AMIS-30622
When reading data from a slave two transmissions are needed. The first transmission consists of 2 bytes of
data. The first byte contains the slave address and the write bit. The second byte contains the address of an
internal register in the AMIS-30622. The internal register address is stored in the circuit RAM. The second
transmission consists of the slave address and the read bit. Then the master can read the data bits on the SDA
line on every rising edge of signal SCK. After each byte of data the master has to acknowledge correct data
reception by pulling SDA to ‘0’. The last byte is not to acknowledge by the master and therefore the slave knows
the end of transmission.
Dump internal address to slave
S Slave address R/W A Internal address A H
‘0’ (write)
Read data from slave
S Slave address R/W A
Data
A
Data
Ab H
‘1’ (read)
Master to slave
Slave to master
N Bytes + acknowledge
S : Start condition
H : Stop condition
A : SDA = ‘0’ ⇔ acknowledge (A)
SDA = ‘1’ ⇔ no acknowledge (Ab)
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