AMIS-30622 Datasheet, PDF (32/42 Pages) AMI SEMICONDUCTOR – I2C Microstepping Motordriver

AMIS-30622
9.2.4. Inter-IC Control (I²C) bus
The I²C interface enabled in the AMIS-30622 uses pins 1 and 2 as Data I/O and Serial Clock respectively.
9.2.4.1. Physical layer
Both SDA and SCK lines are connected to positive supply voltage via a current source or pull-up resistor. When
there is no traffic on the bus both lines are high. Analog glitch filters are implemented to suppress spikes with a
length up to 50 ns.
+ 5V
SDA line
SCK line
SCK_IN
SDA_IN
SCK_OUT
SDA_OUT
AMIS-30622
SCK_IN
SCK_OUT
Master
SDA_IN
SDA_OUT
9.2.4.2. Communication on 2-wire serial bus interface
Each communication starts with a Start condition and ends with a Stop condition. Both conditions are unique and
cannot be confused with data. A high to low transition on the SDA line while SCK is high defines a Start
condition. A low to high transition on the SDA line while SCK is high defines a Stop condition. (see figure
“Start / Stop conditions” below). The master always generates the SCK clock. On every rising transition of SCK
the data on SDA is valid. Data on SDA line is only allowed to change as long as SCK is low.
SDA
SDA
SCK
SCK
START
condition
STOP
condition
data line
stable,
data valid
data change
allowed
Start / Stop Conditions
Bit transfer on 2-wire serial bus interface
Every byte sent on SDA must be 8-bit, with the most significant bit (MSB) transferred first. The number of bytes
that can be transmitted to the AMIS-30622 is restricted to 8 bytes. Each byte is followed by an acknowledge bit,
which is issued by the receiving node (figure below).
SDA
MSB
SCK
1
2
START condition
ACK
7
8
9
1
ACK
9
STOP condition
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