AMIS-49200 Datasheet, PDF (3/19 Pages) AMI SEMICONDUCTOR – Fieldbus MAU Chip

AMIS−49200
RxA
RxS
TxE
TxS
POL
VSS
VSS
VSS
VSS
VSS
VCC
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
AMIS−49200
18
39
Fieldbus MAU
17
40
44pin LQFP
16
41
15
42
14
43
13
44
12
1 2 3 4 5 6 7 8 9 10 11
VSS
VDRV
VSS
CRT
VCC
VDD
VO
SRTR
SRAO
SRSET
SRSETIN
Figure 2. AMIS−49200 Fieldbus MAU Pin Out
Table 1. PIN NUMBERS AND SIGNAL DESCRIPTION
Signal Name
VSS
VREF
VMID
N_PFAIL1
N_PFAIL2
SHSETIN
SHSET
Pin No.
1
2
3
4
5
6
7
I/O
(Note 1)
Ground
AO
AO
AI/O
AI/O
AI
AO
Description
Connect to Ground
Internal bandgap voltage (1.18 V)
2 V bias voltage for AC signals
Power fail alarm at VCC input. This pin is an open-drain output of negative logic.
Power fail alarm at VDD input. This pin is an open-drain output of negative logic.
Feedback (non-inverting) input for the shunt regulator
Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in 5 V voltage
at VCC.
SHUNT
8
VSS/SGND
9
AI
Ground
Control pin of the shunt regulator. Its sink current (25 mA max) is controlled so that the
voltage at SHSETIN is equal to V_REF (1.18 V).
The Current absorbed by SHUNT pin (25 mA max) is fed to this pin, which must be
connected to the ground level.
VSS
10
VSS
11
SRSETIN
12
SRSET
13
Ground
Ground
AI
AO
Ground
Ground
Feedback (inverting) input for the series regulator. The series regulator controls its output
(SRAO) to make this input voltage is equal to V_REF (1.18 V).
Divided voltage of VO output. Feeding this voltage into SRSETIN pin results in 3 V at VO
pin.
SRAO
14
AO
Output pin of an operational amplifier for the series regulator
SRTR
15
AI
Gate of a PMOS transistor for the series regulator
VO
16
AO
Output pin of the series regulator (20 mA max)
VDD
17
Digital Supply Supply voltage input for digital block
1. AI = Analog Input, AO = Analog Output, AI/O = Analog Input/Output, DIS = CMOS Digital Input (Schmitt Trigger), DO = CMOS Digital
Output.
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