AMIS-49200 Datasheet, PDF (11/19 Pages) AMI SEMICONDUCTOR – Fieldbus MAU Chip

AMIS−49200
Voltage Reference
VREFBG
VCC
VREF
2
39 ^VSS
Bandgap
Vref = 1.185 V
(Typ)
Tol. = 2%
VMID Reference
R
237 kW
VREFBG
0.688 R
163.1 kW
VCC
−
A5
+
Vmid
Vmid
3
Bandgap should have its own ground
trace or star connection to system ground.
Figure 6. Bandgap and VMID Voltage Reference
Transmit Block
The transmit block contains four sub-blocks:
1. MDS-interface – decodes input signals to generate
internal control signals.
2. Tri-level Modulator – generates current signals
used as inputs to the slew-rate controller.
3. Slew Rate Controller – converts current to three
distinct VDRV voltage levels (V_S, V_H, V_L).
4. Current Drive Amplifier – op amp designed to
drive current drivers for 31.25 kbps voltage-mode
medium.
MDS-interface
The MDS-interface decodes input signals to generate
internal control signals. The POL pin is used to select the
polarity of TxE (transmit enable). The TxE and TxS
(transmit signal) are the MDS−MAU interface signals.
These three signals are CMOS logic signals powered by the
V_DD supply voltage. When POL is connected to GND, TxE
is assumed to be active high (positive logic). Likewise, if
POL is connected to V_DD, TxE is assumed to be active low
(negative logic). See Table 1 on page 3, Table 11, and
Figure 7 to see how MDS_CTRL Pin 26 can be used to
control MDS interface operation. Table 11 shows the
resulting VDRV output for the various combinations of
interface signals.
Table 11. MDS-INTERFACE LOGIC
POL
TxE
TxS
Low
Low
High
Low
Low
High
High
High
Low
High
Low
High
Low
High
VDRV
V_S
V_H
V_L
V_H
V_L
V_S
MDS_CTRL
26
TXS
37
POL
38
36
TXE
VCC
VMID
−
VDD
+
CMPOUT
VDD
MDS Interface
Inverters powered by VMID to ensure
VDRV goes to Vs = 2.5 V if VDD = 0
(i.e. start-up)
VDD
2p5V_N
VDD
VMID
2p1V
VMID
VCCL
− _{Level Out}
+ ^Shift
N_Vs
VCCL
− _{Level Out N_VL}
+ ^Shift
Tx_enbl
Figure 7. MDS Interface
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