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74HC00 Datasheet, PDF (3/7 Pages) NXP Semiconductors – Quad 2-input NAND gate
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74HC00
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
(V) -55 to 25°C ≤85°C ≤125°C Unit
VIH
Minimum High-Level
Input Voltage
Vout = 0.1V or VCC -0.1V
|Iout| ≤ 20mA
2.0
1.50
1.50
1.50
V
3.0
2.10
2.10
2.10
4.5
3.15
3.15
3.15
6.0
4.20
4.20
4.20
VIL
Maximum Low-Level
Input Voltage
Vout = 0.1V or VCC - 0.1V
|Iout| ≤ 20mA
2.0
0.50
0.50
0.50
V
3.0
0.90
0.90
0.90
4.5
1.35
1.35
1.35
6.0
1.80
1.80
1.80
VOH
Minimum High-Level
Output Voltage
Vin = VIH or VIL
|Iout| ≤ 20mA
2.0
1.9
1.9
1.9
V
4.5
4.4
4.4
4.4
6.0
5.9
5.9
5.9
VOL
Maximum Low-Level
Output Voltage
Vin =VIH or VIL
|Iout| ≤ 2.4mA
3.0
|Iout| ≤ 4.0mA 4.5
|Iout| ≤ 5.2mA 6.0
Vin = VIH or VIL
2.0
|Iout| ≤ 20mA
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34
2.20
3.84
3.70
5.34
5.20
0.1
0.1
V
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| ≤ 2.4mA
3.0
|Iout| ≤ 4.0mA 4.5
|Iout| ≤ 5.2mA 6.0
Iin
Maximum Input Leakage
Vin = VCC or GND
6.0
Current
0.26
0.26
0.26
±0.1
0.33
0.40
0.33
0.40
0.33
0.40
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply Vin = VCC or GND
Current (per Package)
Iout = 0mA
6.0
2.0
20
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High- Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
(V) -55 to 25°C ≤85°C ≤125°C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High- Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Per Buffer)*
22
pF
* Used to determine the no- load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High- Speed CMOS Data Book (DL129/D).
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