LC88FC2H0A Datasheet, PDF (29/48 Pages) ON Semiconductor – 16-bit Microcontroller

LC88FC2H0A
Parameter
Stop condition
setup time
Data hold time
Data setup time
Symbol
tSU;STO
Applicable
Pin/Remarks
Conditions
SM0CK (P22)  See Fig. 8.
SM0DA (P23)
VDD [V]
Specification
min
typ max unit
1.0
Tfilt
tSU;STOx
tHD;DAT
SM0CK (P22)
SM0DA (P23)
SM0CK (P22)
SM0DA (P23)
 Standard clock mode
 Specified as interval up to
time when output state starts
changing.
 High-speed clock mode
 Specified as interval up to
time when output state starts
changing.
 See Fig. 8.
2.7 to 3.6
tHD;DATx SM0CK (P22)  Specified as interval up to ^{2.7 to 3.6}
SM0DA (P23) ^{time when output state starts}
changing.
tSU;DAT SM0CK (P22)  See Fig. 8.
SM0DA (P23)
tSU;DATx
SM0CK (P22)
SM0DA (P23)
 Specified as interval up to
time when output state starts
changing.
2.7 to 3.6
tF
SM0CK (P22)  See Fig. 8.
SM0DA (P23)
2.7 to 3.6
4.9
1.1
0
1
1
1tSCL-
1.5Tfilt
μsec
Tfilt
1.5
Tfilt
300
SM0CK and
tF
SM0DA pins fall
time
SM0CK (P22)  When SMIIC register
SM0DA (P23) ^{control bits}
PSLW  1, P5V  1
3
20+0.1Cb
250
ns
 SM0CK, SM0DA port
output FAST mode
3.0 to 3.6
100
 Cb  400pF
Note 4-8-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-8-2 : The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
0
0
1
1
BRP0
0
1
0
1
Tfilt
tCYC1
tCYC2
tCYC3
tCYC4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range :
250 ns  Tfilt  140 ns
Note 4-8-3 : Cb represents the total loads (in pF) connected to the bus pins. Cb  400pF
Note 4-8-4 : The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows :
250 ns  Tfilt  140 ns
BRDQ (bit5) = 1
SCL frequency setting  100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows :
250 ns  Tfilt  140 ns
BRDQ (bit5) = 0
SCL frequency setting  400kHz
No.A2183-29/48