LC89057W-VF4A-E Datasheet, PDF (28/59 Pages) Sanyo Semicon Device – Digital Audio Interface Transceiver

LC89057W-VF4A-E
10.4.6 Processing during error recovery
• _{When preambles B, M, and W are detected, PLL becomes locked and data demodulation begins.}
• _{RDATA output data is output from the RLRCK edge after RERR turns to "L".}
45ms to 300ms
RERR
Internal lock signal
OK
RLRCK
RDATA
Data
Output start from RLRCK edge
immediately after RERR flag is lowered
Figure 10.12 Data processing when data demodulation starts
10.5 Channel Status Data Output _{________}
10.5.1 Data delimiter bit 1 output ( AUDIO )
____________
____________
• _{AUDIO outputs bit 1 of the channel status that indicates whether the input bi-phase data is PCM audio data. AUDIO is}
immediately output upon detection of RERR even during "H" output period.
• _{OR-output with IEC61937 or with the DTS-CD/LD detection flag is also possible with AOSEL.}
______
AUDIO
L
H
____________
Table 10.6 AUDIO Output
Output Conditions
PCM audio data (CS bit 1 = "L")
Non-audio data (CS bit 1 = "H")
10.5.2 Emphasis information output (EMPHA)
• _{EMPHA outputs shows whether there are 50/15μs emphasis parameters for consumer and broadcast studio.}
EMPHA is immediately output upon detection of RERR even during "H" output.
EMPHA
L
H
Table 10.7 EMPHA Output
Output Conditions
No pre-emphasis
50/15μs pre-emphasis
No.7202-28/59