LC89057W-VF4A-E Datasheet, PDF (16/59 Pages) Sanyo Semicon Device – Digital Audio Interface Transceiver

LC89057W-VF4A-E
10.1.5 Points to notice about switching clock source while PLL is locked
• _{In the state where the PLL is locked, if the clock is switched to XIN source with SELMTD, OCKSEL, and RCKSEL}
while the oscillator amplifier is stopped (initial setting), clock continuity is maintained but RERR temporarily outputs
an error (high level) indication. When switched to XIN source, the oscillator amplifier is switched to the operating
state at the same time. Consequently the input fs calculation restarts. At this time, the previous fs calculation value is
reset and compared with the newly calculated fs value. Then those two values are found not identical, that’s why the
error is temporarily issued.
• _{The following settings are required to switch the clock source with SELMTD, OCKSEL, and RCKSEL without}
changing the RERR status while PLL is locked.
(1) Set the oscillation amplifier to the continuous operation mode with AMPOPR[1:0].
(2) Set with FSERR to the mode where fs change is not reflected to the error flag.
• _{By one of the above settings, changing of the RERR status can be constrained when the clock source is switched with}
SELMTD, OCKSEL, and RCKSEL.
• _{When switching the clock source to XIN from the state where the oscillation amplifier is stopped while the PLL is}
locked, the output clock using XIN as the source starts being output after the oscillation amplifier starts operating.
When the PLL is locked, switching of the clock source from XIN to PLL is performed instantaneously. In either case,
clock continuity is maintained.
10.1.6 Master clock block diagram (TMCK, XIN, XOUT, RMCK, XMCK)
• _{The relationships between the three master clocks, switching, and the frequency division function, are described below.}
• _{The contents in the square brackets [∗∗∗] by the switch and function blocks correspond to the write command names.}
• _{Lock/Unlock is automatically switched by PLL locking/unlocking.}
[PLLOPR]
[PLLSEL]
Selected Biphase
PLL
(256fs or 512fs)
[EXSYNC]
TMCK (I) 256fs or 512fs
XIN (I)
XOUT (O)
[AMPOPR0]
[AMPOPR1]
[XINSEL]
1/N
(N=1, 2)
[XMSEL0]
[XMSEL1]
1/N
(N=1, 2)
[PRSEL0]
[PRSEL1]
1/N
(N=1, 2, 4)
Lock /Unlock
RMCK (O)
[XRSEL0]
[XRSEL1]
1/N
(N=1, 2, 4)
[SELMTD]
[OCKSEL]
[RCKSEL]
XMCK (O)
Figure 10.2 Master Clock Block Diagram
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