AMIS-30512 Datasheet, PDF (24/30 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30512
SPI Control Registers
All SPI control registers have Read/Write access and default to “0” after power−on or hard reset.
Table 12. SPI Control Register WR
Control Register (WR)
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
Reset
0
0
0
0
0
0
0
0
Data
WDEN
WDT[3:0]
−
−
−
Where:
R/W
Reset:
WDEN:
WDT[3:0]:
Read and Write access
Status after power-On or hard reset
Watchdog enable. Writing “1” to this bit will activate the watchdog timer (if not enabled yet) or will clear
this timer (if already enabled). Writing “0” to this bit will clear WD bit (SPI Status Register 0).
Watchdog timeout interval
Table 13. SPI Control Register 0
Control Register 0 (CR0)
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
01h
Reset
0
0
0
0
0
0
0
0
Data
SM[2:0]
CUR[4:0]
Where:
R/W
Reset:
SM[2:0]:
CUR[4:0]:
Read and Write access
Status after power−On or hard reset
Step mode
Current amplitude
Table 14. SPI Control Register 1
Control Register 1 (CR1)
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Access
R/W
R/W
R/W
R/W
R/W
02h
Reset
0
0
0
0
0
Data
DIRCTRL
NXTP
−
−
PWMF
Where:
R/W
Reset:
DIRCTRL
NXTP
PWMF
PWMJ
EMC[1:0]
Read and Write access
Status after power−on or hard reset
Direction control
NEXT polarity
PWM frequency
PWM jitter
EMC slope control
Bit 2
R/W
0
PWMJ
Bit 1
Bit 0
R/W
R/W
0
0
EMC[1:0]
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