AMIS-30512 Datasheet, PDF (19/30 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30512
not properly connected to guarantee sufficient low Rdson of
the drivers, then the bit <CPFAIL> is set in Table 27: SPI
Status Register 0. Also after power−on−reset the charge
pump voltage will need the time t_CPU to exceed the required
threshold. During that time <CPFAIL> will be set to “1”.
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
<OVCYij> OR <OPENi> OR <CPFAIL>
Logic Supply Regulator
AMIS-30512 has an on-chip 5 V low-drop regulator with
external decoupling capacitor to supply the digital part of the
VBB
chip, some low-voltage analog blocks and external circuitry.
The voltage is derived from an internal bandgap reference.
To calculate the available drive-current for external
circuitry, the specified I_load should be reduced with the
consumption of internal circuitry (unloaded outputs) and the
loads connected to logic outputs. See DC parameters.
Power-On Reset (POR) Function
The open drain output pin POR/WD provides an “active
low” reset for external purposes. At power-up of
AMIS-30512, this pin will be kept low for some time to reset
for example an external microcontroller. A small analog
filter avoids resetting due to spikes or noise on the VDD
supply.
VDD
t_PU
t
t_PD
V_DDH
V_DDL
t
< t_RF
POR/WD pin
t_POR
t_RF
Figure 14. Power−on−Reset Timing Diagram
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (Table 12: SPI Control Register WR). Once
this bit has been set to “1” (watchdog enable), the
microcontroller needs to re-write this bit to clear an internal
timer before the watchdog timeout interval expires. In case
the timer is activated and WDEN is acknowledged too early
(before t_WDPR) or not within the interval (after t_WDTO), then
a reset of the microcontroller will occur through POR/WD
pin. In addition, a warm/cold boot bit <WD> is available in
SPI Status Register 0 for further processing when the
external microcontroller is alive again. The watchdog reset
delay t_WDRD is determined by an internal delay of 0,5 ms
added to an external delay formed by the pull up resistance
and the capacitive load on the POR/WD pin.
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