AMIS-30512 Datasheet, PDF (20/30 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30512
VBB
VDD
t_PU
V_DDH
POR/WD pin
t_POR
t_DSPI
Enable WD
> t_WDPR or < t_WDTO
Acknowledge WD
t
t_WDTO
t
t
t_WDRD
= t_WDPR or = t_WDTO
t_POR
WD timer
t
Figure 15. Watchdog Timing Diagram
NOTE: t_DSPI is the time needed by the external microcontroller to shift-in the <WDEN> bit after a power-up.
The duration of the watchdog timeout interval is
programmable through the WDT [3:0] bits (Table 12: SPI
Control Register WR). The timing is given in Table 11.
Table 11. Watchdog Timeout Interval as Function of
WDT[3.0]
Index
0
WDT[3:0]
0000
t_WDTO (ms)
32
1
0001
64
2
0010
96
3
0011
128
4
0100
160
5
0101
192
6
0110
224
7
0111
256
8
1000
288
9
1001
320
A
1010
352
B
1011
384
C
1100
416
D
1101
448
E
1110
480
F
1111
512
CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30512, the input
CLR needs to be pulled to logic 1 during minimum time
given by T_CLR. (Table 5: AC Parameters) This reset function
clears all internal registers without the need of a
power−cycle. The operation of all analog circuits is
depending on the reset state of the digital, charge pump
remains active. Logic 0 on CLR pin resumes normal
operation again.
Sleep Mode
The bit <SLP> in Table 15: SPI Control Register 2 is
provided to enter a so−called “sleep mode”. This mode
allows reduction of current−consumption when the motor is
not in operation. The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• Pulses on NXT and DIR inputs are ignored
• SPI communication remains possible (slight current
increase during SPI communication)
• Reset of chip is possible through CLR pin
• Oscillator and digital clocks are silent, except during
SPI communication
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time t_CPU is needed for the charge pump
to stabilize. After this time, NXT commands can be issued.
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