AND8054 Datasheet, PDF (19/28 Pages) ON Semiconductor – Designing RC Oscillator Circuits with Low Voltage Operational Amplifiers and Comparators for Precision Sensor Applications

AND8054/D
The voltage limit circuit shown in Figure 21 is useful in
dual power supply designs when the integrator capacitance
is relatively small. A combination of two transistors and two
diodes are used to make up the circuit, which limits the
signal at positive and negative voltages. The diodes are used
to reduce the effective capacitance of the bipolar transistors
and they can be removed for low voltage applications.
The operation of the limit circuits formed by the NPN
and/or PNP transistors can be understood by using the
Ebers–Moll transistor model, where a transistor is modeled
as a base–to–emitter and a base–to–collector diode. The
circuit functions by setting the fixed voltage at the
base–to–collector junction to be less than the diode’s
turn–on voltage; therefore, this diode is always “OFF’’.
Next, the emitter of the transistor is connected to the sine
wave output of the amplifier; thus, the base–to–emitter
voltage (V_BE) can be either greater than or less than a diode’s
turn–on voltage. When the V_BE voltage is above the diode’s
turn–on voltage, the diode is “ON’’ and the transistor is in
the forward–active mode of operation and the circuit clamps
at a level set by the base voltage. However, when the V_BE
voltage is below the diode turn–on voltage, the junction is
“OFF’’ and the transistor is in the cut–off mode of operation
and the clamping network is effectively an open circuit.
V_{Q1_Base}
D1
Q1
V_{Q2_Base}
D2
Q2
V_{IN R}
C
V_CC
–
+
V_EE
V_OUT
VQ1_Base u 0 V
VQ2_Base t 0 V
VPos_Limit + VQ1_base ) VQ1_base–to–emitter ) Vf
^ VQ1_base ) (2 * 0.7) ^ VQ1_base ) 1.4 V
VNeg_Limit + VQ2_base * VQ2_base–to–emitter * Vf
^ VQ2_base * (2 * 0.7) ^ VQ2_base * 1.4 V
Figure 21. Dual Power Supply Limit Circuit
Single Power Supply Circuits
Figure 22 shows the clamping function of the limit circuit
for a single power supply application [3] [4]. The limit
circuit for low voltage single supply circuits can be formed
by a single NPN or PNP transistor. The PNP circuit shown
in Figure 23 is used to create the maximum voltage limit,
while the NPN circuit shown in Figure 24 is used to form the
minimum voltage limit. Note that in single supply
applications it is not necessary to use both the PNP and NPN
limit circuits. Only one of the limit circuits is required to
prevent the amplifiers from saturating in the state variable
oscillator.
V_IN and V_OUT
V_IN
V_{Max_Limit}
V_OUT
V_{Min_Limit}
t
Figure 22. Single Power Supply Clamping
V_{Q1_Base}
Q1
R
V_IN
C
V_CC
V_CC/2
–
+
V_EE
V_OUT
VMax_Limit + VQ1_base ) VQ1_base–to–emitter
^ VQ1_base ) 0.7 V
Figure 23. Single Supply Maximum Limit Circuit
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