LC786800E Datasheet, PDF (15/26 Pages) Sanyo Semicon Device – Compressed Audio signal Processor IC with USB host controller

LC786800E
Communication Timing specification between Host controller
SIFCE
(Input)
SIFCK
(Input)
SIFDI
(Input)
SIFDO
(Output)
BUSYB
(Output)
tCSU
1/fCLK
tCKH tCKL
tCWSU tCWHD
tCDON
tCDOH
tCHD
tCRAS
tCE
tCDOF
tCBST
Parameter
Symbol
Pin names
min
typ
max
unit
SIFCK clock frequency
fCLK
SIFCK
3.3
0.725
MHz
150
SIFCK clock "H" level width
tCKH
SIFCK
690
ns
150
SIFCK clock "L" level width
tCKL
SIFCK
690
ns
0
Transfer start enable time
tCE
BUSYB, SIFCE
0
ns
100
Setup time for transfer start
tCSU
SIFCE, SIFCK
200
ns
100
Hold time for transfer end
tCHD
SIFCE, SIFCK
200
ns
Setup time for SIFDI
tCWSU
SIFDI, SIFCK
75
75
ns
Hold time for SIFDI
tCWHD
SIFDI, SIFCK
75
200
ns
Output delay time for SIFDO “H”
tCDOH
SIFDO, SIFCK
100
350
ns
Output delay time for SIFDO
tCRAS
SIFDO, SIFCK
100
350
ns
Turn on time for SIFDO *1
tCDON
SIFDO, SIFCE
100
100
ns
Turn off time for SIFDO *1
tCDOF
SIFDO, SIFCE
150
150
ns
BUSYB "L" level output delay time
tCBST
BUSYB
150
350
ns
Internal CPU operating speed mode Upper step : Normal speed
Lower step : Low speed
*1: The tCDON and tCDOF specifications are for when the SIFDO pin is set to the 3-State mode.
No.A2082-15/26