CAT28F001G-12TE13 Datasheet, PDF (15/18 Pages) ON Semiconductor – 1 Megabit CMOS Boot Block Flash Memory

CAT28F001
ALTERNATE CE-CONTROLLED WRITES
V_CC = +5V ±10%, unless otherwise specified
JEDEC
Symbol
tAVAV
tAVEH
tEHAX
tDVEH
tEHDX
tWLEL
t_EHWH
tELEH
tEHEL
Standard
Symbol
tWC
tAS
tAH
tDS
tDH
tWS
tWH
tCP
tEPH
Parameter
Write Cycle Time
Address Setup to CE Going High
Address Hold Time from CE Going High
Data Setup Time to CE Going High
Data Hold Time from CE Going High
WE Setup Time to CE Going Low
WE Hold Time from CE Going High
CE Pulse Width
CE High Pulse Width
28F001-90
Min Max
90
40
10
40
10
0
0
40
10
tEHGL
—
Write Recovery Time Before Read
0
tPHEL
tPS(1)
RP High Recovery to CE Going Low
480
tPHHEH
tPHS(1)
RP VHH Setup to CE Going High
100
tVPEH
t_VPS(1)
V_PP Setup to CE Going High
100
t_EHQV1
—
Duration of Programming Operations
15
tEHQV2
—
Duration of Erase Operations (Boot)
1.3
tEHQV3
—
Duration of Erase Operations (Parameter) 1.3
tEHQV4
—
Duration of Erase Operations (Main)
3
tQVVL
tVPH⁽¹⁾
VPP Hold from Valid Status Reg Data
0
tQVPH
tPHH(1)
RP VHH Hold from Status Reg Data
0
tPHBR(1)
—
Boot Block Relock Delay
100
tGHHWL
—
OE VHH Setup to WE Going Low
480
tWHGH
—
OE VHH Hold from WE High
480
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
28F001-12
Min Max
120
40
10
40
10
0
0
40
10
0
480
100
100
15
1.3
1.3
3
0
0
100
480
480
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
Sec
Sec
Sec
ns
ns
ns
ns
ns
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-1078, Rev. K