CAT28F001G-12TE13 Datasheet, PDF (11/18 Pages) ON Semiconductor – 1 Megabit CMOS Boot Block Flash Memory

CAT28F001
IN-SYSTEM OPERATION
For on-board programming, the RP pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, RP must
transition to VHH. Hold RP at this high voltage throughout
the program or erase interval (until after Status Register
confirm of successful completion). At this time, it can
return to VIH or VIL.
Figure 4 Byte Programming Flowchart
START
WRITE 40H,
BYTE ADDRESS
WRITE BYTE
ADDRESS/DATA
READ STATUS
REGISTER
SR.7 = 1?
NO
YES
FULL STATUS
CHECK IF DESIRED
BYTE PROGRAM
COMPLETED
FULL STATUS CHECK PROCEDURE
Bus
Operation Command Comments
Write
Program
Setup
Data = 40H
Address = Bytes to be Programmed
Write
Program
Data to be programmed
Address = Byte to be Programmed
Read
Status Register Data.
Toggle OE or CE to update
Status Register
Check SR.7
Standby
1 = Ready, 0 = Busy
Repeat for subsequent bytes.
Full Status check can be done after each byte or after a sequence
of bytes.
Write FFH after the last byte programming operation to reset the
device to Read Array Mode.
STATUS REGISTER DATA
READ (SEE ABOVE)
SR.3 = 0?
NO
V_PP RANGE
ERROR
YES
SR.4 = 0?
NO BYTE PROGRAM
ERROR
YES
BYTE PROGRAM
SUCCESSFUL
Bus
Operation Command Comments
Standby
Check SR.3
1 = V_PP Low Detect
Standby
Check SR.3
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program attempt, before
further attempts are allowed by the Write State Machine.
SR.3 is only cleared by the Clear Status Register Command, in
case where multiple bytes are programmed before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-1078, Rev. K