CAT28F001G-12TE13 Datasheet, PDF (14/18 Pages) ON Semiconductor – 1 Megabit CMOS Boot Block Flash Memory

CAT28F001
Figure 7. A.C. Timing for Program/Erase Operation
VCC POWER-UP
& STANDBY
VIH
ADDRESSES (A)
VIL
VIH
CE (E)
WRITE
WRITE PROGRAM OR _{VALID ADDRESS & DATA (PROGRAM)} AUTOMATED PROGRAM
ERASE SETUP COMMAND _{OR ERASE CONFIRM COMMAND}
OR ERASE DELAY
AIN
tAVAV
AIN
tAVWH
tWHAX
VIL
VIH
OE (G)
VIL
VIH
tELWL
tWHEH
tWHWL
tWHGL
tWHQV 1, 2, 3, 4
WE (W)
VIL
tWLWH
VIH
HIGH Z
tDVWH
tWHDX
DATA (I/O)
DIN
DIN
VIL
tPHWL
VHH
tPHHWH
6.5V
RP (P) ^VIH
VIL
VPPH
tVPWH
VPP (V)VPVPIHL
VIL
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
VALID
SRD
DIN
tQVPH
tQVVL
POWER UP/DOWN PROTECTION
The CAT28F001 offers protection against inadvertent
programming during V_PP and V_CC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, V_PP and V_CC
may power up in any order. Additionally V_PP may be
hardwired to V_PPH independent of the state of V_CC and
any power up/down cycling. The internal command
register of the CAT28F001 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between V_CC and V_SS and V_PP and V_SS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Doc. No. MD-1078, Rev. K
14
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice