LC79451KB Datasheet, PDF (11/38 Pages) ON Semiconductor – Controller and Driver

LC79451KB
5-6. SPI (3-wire serial interface) Timing Characteristics
(Case without the special mention VDD = +2.5V, VSS = 0V, Ta = +25°C)
Parameter
Symbol
Conditions
min
typ
max
Unit
SCL frequency
fSCL(2)
VDD = 1.6V to 2.0V
VDD = 2.0V to 3.6V
-
-
6
MHz
-
-
10
MHz
CS - SCL setup time
tSU(8)
300
-
-
ns
SCL - CS hold time
tHD(5)
300
-
-
ns
SDA - SCL setup time
tSU(9)
50
-
-
ns
SCL - SDA hold time
tHD(6)
50
-
-
ns
SCL low pulse width
tPW(4)
50
-
-
ns
SCL high pulse width
tPW(5)
50
-
-
ns
CS interval time
tINT(1)
1000
-
-
ns
1) SPI interface bus timing
CS
(10%)
SCL _(50%)
tSU(8)
tPW(4)
tPW(5)
(90%)
tINT(1)
tHD(5)
SDA (50%)
(A7) (A6)
tSU(9)
tHD(6)
(D1) (D0)
Fig.7. SPI bus timing
2) Timing of BUSY and START Flag after setting START command in SPI interface
Output of BUSY means START Flag. During in BUSY=1, “WAVEFORM PARAMETER” and “CONTROL
REGISTER” are write inhibit state. An internal state is charge-pump rising period before the waveform output or
during the waveform output. After outputs waveform from segment, BUSY and START FLAG are automatically
canceled. (Cf. 6-3)
CS
SCL
BUSY
START Flag
*2
*1
*1 Automatic charge-pump mode : charge-pump rising period (set to control register 1) + waveform
output period (set to waveform parameter)
Manual charge-pump mode : waveform output period (set to waveform parameter)
*2 BUSY and START FLAG are automatically canceled.
Fig.8. SPI BUSY output, and START Flag timing
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