AMIS-30585 Datasheet, PDF (11/17 Pages) AMI SEMICONDUCTOR – S-FSK PLC Modem

AMIS−30585
Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on
the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 8. OSCILLATOR
Parameter
Description
Condition
Min.
Max.
Unit
f_CLK
Crystal frequency
(Note 8)
24 MHz
−100 ppm
24 MHz
+100 ppm
Duty cycle with quartz connected
(Note 8)
30
70
%
T_startup
Start−up time
(Note 8)
50
Ms
CL_XOUT
Maximum Capacitive load on XOUT XIN used as clock input
50
pF
VIL_XOUT
Low input threshold voltage
XIN used as clock input
−0.3 VDD
V
VIH_XOUT High input threshold voltage
XIN used as clock input
0.7 vdd
V
VOL_XOUT Low output voltage
XIN used as clock input, XOUT = 2 mA
0.3
V
VOH_XOUT High input voltage
XIN used as clock input
VDD−0.3
V
8. For the design of the oscillator crystal parameters have been taken from the data sheet [8]. The series loss resistance for this type of crystal
is maximum 50 W. However the oscillator cell has been designed with some margin for series loss resistance up to 80 W.
Table 9. ZERO CROSSING DETECTOR AND 50/60HZ PLL: Pin M50HZ_IN
Parameter
Description
Condition
Min.
Max.
Unit
Imaxp
M50HZIN
Maximum peak input current
−20
20
mA
Imaxavg
M50HZIN
Maximum average input current
during 1 ms
−2
2
mA
V_MAINS
Mains voltage (ms) range
With protection resistor at M50HZIN
90
VIRM_50HZIN Rising threshold level
(Note 9)
VIFM_50HZIN Falling threshold level
(Note 9)
0.9
VHY_50HZIN
Hysteresis
(Note 9)
0.4
Flock_50Hz
Lock range for 50 Hz (Note 10)
MAINS_FREQ = 0 (50 Hz)
45
Flock_60Hz
Lock range for 60 Hz (Note 10)
MAINS_FREQ = 0 (60 Hz)
54
Tlock_50Hz
Lock time (Note 10)
MAINS_FREQ = 0 (50 Hz)
Tlock_60Hz
Lock time (Note 10)
MAINS_FREQ = 0 (60 Hz)
DF_60Hz
Frequency variation without going
out of lock (Note 10)
MAINS_FREQ = 0 (50 Hz)
550
V
1.9
V
V
V
55
Hz
66
Hz
10
S
10
S
0.1
Hz/s
DF_50Hz
Frequency variation without going
out of lock (Note 10)
MAINS_FREQ = 0 (60 Hz)
0.1
Hz/s
Jitter_{CHIP_CLK} Jitter of CHIP_CLK (Note 10)
−60
60
ms
9. Measured relative to VSS.
10. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.
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