CAT5409WI-25 Datasheet, PDF (10/16 Pages) ON Semiconductor – Quad Digitally Programmable Potentiometers with 64 Taps and I²C Interface

CAT5409
position), to a Data Register is a write to non-volatile
memory and takes a minimum of t_WR to complete. The
transfer can occur between one of the four poten-
tiometers and one of its associated registers; or the
transfer can occur between all potentiometers and
one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5409; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the CAT5409 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby providing a fine tuning capability to the host.
For each SCL clock pulse (t_HIGH) while SDA is HIGH,
the selected wiper will move one resistor segment
towards the R_H terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the R_L terminal.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0101
S ^{ID3 ID2 ID1 ID0} A3 A2 A1 A0 A I3 I2 I1 I0 R1 R0 P1 P0 A ^S
T
C
CT
A
R
T
Device ID
Internal
Address
K
Instruction
Opcode
KO
Register Pot/WCR ^P
Address Address
Figure 8. Three-Byte Instruction Sequence
SDA
0 101
S
T
ID3 ID2 ID1 ID0 A3
A
R Device ID
T
A2 A1 A0
Internal
Address
A I3
C
K
I2 I1 I0
Instruction
Opcode
R1 R0 P1 P0 A
C
K
Data Pot/WCR
Register Address
Address
D7 D6 D5 D4 D3 D2 D1 D0 A S
CT
WCR[7:0]
KO
P
or
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
SDA
0101
ID3 ID2 ID1 ID0
S
A3
A2 A1 A0
A ^I3
I2 I1 I0 R1 R0 P1 P0 _A
I
I
T
C
CN N
A Device ID
Internal
K
Instruction Data Pot/WCR K C C
R
Address
Opcode
Register ^Address
12
T
Address
ID
NE
CC
n1
DS
ET
CO
nP
Doc. No. MD-2010 Rev. L
10
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice