NSS60100DMT Datasheet, PDF (1/6 Pages) ON Semiconductor – 60 V, 1 A, Low VCE(sat) PNP Transistors

NSS60100DMT
60 V, 1 A, Low V_CE(sat) PNP
Transistors
ON Semiconductor’s e²PowerEdge family of low V_CE(sat)
transistors are miniature surface mount devices featuring ultra low
saturation voltage (V_CE(sat)) and high current gain capability. These
are designed for use in low voltage, high speed switching applications
where affordable efficient energy control is important.
Typical applications are DC−DC converters and LED lightning,
power management…etc. In the automotive industry they can be used
in air bag deployment and in the instrument cluster. The high current
gain allows e²PowerEdge devices to be driven directly from PMU’s
control outputs, and the Linear Gain (Beta) makes them ideal
components in analog amplifiers.
Features
• NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• NSV60100DMTWTBG − Wettable Flanks Device
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T_A = 25°C)
Rating
Symbol Max Unit
Collector−Emitter Voltage
V_CEO
60 Vdc
Collector−Base Voltage
V_CBO
60 Vdc
Emitter−Base Voltage
V_EBO
6
Vdc
Collector Current − Continuous
I_C
1
A
Collector Current − Peak
I_CM
2
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Characteristic
Symbol Max Unit
Thermal Resistance Junction−to−Ambient
(Notes 1 and 2)
R_qJA
55 °C/W
Total Power Dissipation per Package @
T_A = 25°C (Note 2)
Thermal Resistance Junction−to−Ambient
(Note 3)
P_D
R_qJA
2.27 W
69 °C/W
Power Dissipation per Transistor @ T_A = 25°C
P_D
1.8
W
(Note 3)
Junction and Storage Temperature Range
T_J, T_stg −55 to °C
+150
1. Per JESD51−7 with 100 mm² pad area and 2 oz. Cu (Dual Operation).
2. P_D per Transistor when both are turned on is one half of Total P_D or 1.13 Watts.
3. Per JESD51−7 with 100 mm² pad area and 2 oz. Cu (Single−Operation).
www.onsemi.com
60 Volt, 1 Amp
PNP Low V_CE(sat) Transistors
MARKING
DIAGRAM
1
6
WDFN6
2 ^{AP MG} 5
1
CASE 506AN
3^G
4
AP = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
ORDERING INFORMATION
Device
Package Shipping^†
NSS60100DMTTBG
WDFN6 3000/Tape &
(Pb−Free)
Reel
NSV60100DMTWTBG WDFN6 3000/Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 1
Publication Order Number:
NSS60100DMT/D