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NSBC114EPDXV6T1G Datasheet, PDF (1/14 Pages) ON Semiconductor – Dual Bias Resistor Transistors | |||
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NSBC114EPDXV6T1G,
NSBC114EPDXV6T5G
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a baseâemitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBC114EPDXV6T1
series, two complementary BRT devices are housed in the SOTâ563
package which is ideal for low power surface mount applications
where board space is at a premium.
Features
⢠Simplifies Circuit Design
⢠Reduces Board Space
⢠Reduces Component Count
⢠Available in 8 mm, 7 inch Tape and Reel
⢠These are PbâFree Devices
MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1
and Q2, â minus sign for Q1 (PNP) omitted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
Collector Current
IC
100
mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
PD
357
mW
2.9
mW/°C
Thermal Resistance (Note 1)
Junction-to-Ambient
RqJA
°C/W
350
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
PD
500
mW
4.0
mW/°C
Thermal Resistance (Note 1)
Junction-to-Ambient
RqJA
250
°C/W
Junction and Storage Temperature
TJ, Tstg â55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FRâ4 @ Minimum Pad
http://onsemi.com
(3)
(2)
(1)
R1
R2
Q1
Q2
R2
R1
(4)
(5)
(6)
6
1
SOTâ563
CASE 463A
PLASTIC
MARKING DIAGRAM
xx MG
G
xx = Specific Device Code
(see table on page 2)
M = Date Code
G = PbâFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shippingâ
NSBC114EPDXV6T1G SOTâ563 4 mm pitch
4000/Tape & Reel
NSBC114EPDXV6T5G SOTâ563 2 mm pitch
8000/Tape & Reel
â For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
1
November, 2008 â Rev. 5
Publication Order Number:
NSBC114EPDXV6/D
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