 English |
|
|
|
|
|
|
|
| 74HC73 Datasheet, PDF (9/16 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger | |||
| |||
| ◁ |
NXP Semiconductors
74HC73
Dual JK ï¬ip-ï¬op with reset; negative-edge trigger
Table 8.
Type
74HC73
Measurement points
Input
VI
VCC
VM
0.5VCC
Output
VM
0.5VCC
VI 90 %
negative
pulse
GND
VI
positive
pulse
10 %
GND
VM
10 %
tf
tr
90 %
VM
VI
G
RT
tW
tW
VCC
DUT
VM
tr
tf
VM
VO
CL
001aah768
Fig 8.
Test data is given in Table 9.
Deï¬nitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
74HC73
VCC
tr, tf
6 ns
Load
CL
15 pF, 50 pF
74HC73_4
Product data sheet
Rev. 04 â 19 March 2008
© NXP B.V. 2008. All rights reserved.
9 of 16
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese