74HC73 Datasheet, PDF (7/16 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger

NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); C_L = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max
Min
Max
t_h
hold time
nJ, nK to nCP; see Figure 6
V_CC = 2.0 V
3 −8 -
3
3
- ns
V_CC = 4.5 V
3 −3 -
3
-
3
- ns
V_CC = 6.0 V
3 −2 -
3
-
3
ns
f_max
maximum
nCP input; see Figure 6
frequency
V_CC = 2.0 V
6.0 23 - 4.8
4.0
- MHz
V_CC = 4.5 V
V_CC = 6.0 V
30 70 -
24
-
20
- MHz
35 83 -
28
-
24
- MHz
V_CC = 5.0 V; C_L = 15 pF
- 77 -
-
- MHz
C_PD
power
per flip-flop;
dissipation V_I = GND to V_CC
capacitance
[3] _{- 30 -}
-
-
-
- pF
[1] t_pd is the same as t_PHL, t_PLH.
[2] t_t is the same as t_THL, t_TLH.
[3] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + ∑(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in V;
N = number of inputs switching;
∑(C_L × V_CC2 × f_o) = sum of outputs.
74HC73_4
Product data sheet
Rev. 04 — 19 March 2008
© NXP B.V. 2008. All rights reserved.
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