74HC73 Datasheet, PDF (6/16 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger

NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); C_L = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max
Min
Max
t_pd
propagation nCP to nQ; see Figure 6
[1]
delay
V_CC = 2.0 V
- 52 160 -
200
-
240 ns
V_CC = 4.5 V
- 19 32
-
40
-
48 ns
V_CC = 6.0 V
- 15 27
-
34
-
41 ns
V_CC = 5.0 V; C_L = 15 pF
- 16 -
-
-
-
- ns
nCP to nQ; see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
V_CC = 5.0 V; C_L = 15 pF
nR to nQ, nQ; see Figure 7
- 52 160 -
200
-
240 ns
- 19 32
-
40
-
48 ns
- 15 27
34
-
41 ns
- 16 -
-
ns
V_CC = 2.0 V
- 50 145 -
180
-
220 ns
V_CC = 4.5 V
- 18 29
-
36
-
44 ns
V_CC = 6.0 V
- 14 25
31
-
38 ns
V_CC = 5.0 V; C_L = 15 pF
- 15 -
-
-
-
- ns
t_t
transition time nQ, nQ; see Figure 6
[2]
V_CC = 2.0 V
- 19 75
-
95
-
110 ns
V_CC = 4.5 V
- 7 15
-
19
-
22 ns
V_CC = 6.0 V
- 6 13
16
-
19 ns
t_W
pulse width nCP input, HIGH or LOW;
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
nR input, HIGH or LOW;
see Figure 7
80 22 - 100
120
- ns
16 8 -
20
-
24
- ns
14 6 -
17
-
20
ns
V_CC = 2.0 V
80 22 - 100
120
- ns
V_CC = 4.5 V
16 8 -
20
-
24
- ns
V_CC = 6.0 V
14 6 -
17
-
20
ns
t_rec
recovery time nR to nCP; see Figure 7
V_CC = 2.0 V
80 22 - 100
120
- ns
V_CC = 4.5 V
16 8 -
20
-
24
- ns
V_CC = 6.0 V
14 6 -
17
-
20
ns
t_su
set-up time nJ, nK to nCP; see Figure 6
V_CC = 2.0 V
80 22 - 100
120
- ns
V_CC = 4.5 V
16 8 -
20
-
24
- ns
V_CC = 6.0 V
14 6 -
17
-
20
ns
74HC73_4
Product data sheet
Rev. 04 — 19 March 2008
© NXP B.V. 2008. All rights reserved.
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