74HC73 Datasheet, PDF (4/16 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger

NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
6. Functional description
Table 3. Function table^[1]
Input
Output
nR
nCP
nJ
nK
nQ
nQ
L
X
X
X
L
H
H
↓
h
h
q
q
H
↓
l
h
L
H
H
↓
h
l
H
L
H
↓
l
l
q
q
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
↓ = HIGH-to-LOW clock transition.
7. Limiting values
Operating mode
asynchronous reset
toggle
load 0 (reset)
load 1 (set)
hold (no change)
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
V_CC
supply voltage
I_IK
input clamping current
V_I < −0.5 V or V_I > V_CC + 0.5 V
I_OK
output clamping current
V_O < −0.5 V or V_O > V_CC + 0.5 V
I_O
output current
V_O = −0.5 V to V_CC + 0.5 V
−0.5 +7.0
V
[1] _-
±20
mA
[1] _-
±20
mA
-
±25
mA
I_CC
I_GND
T_stg
P_tot
supply current
ground current
storage temperature
total power dissipation
T_amb = −40 °C to +125 °C
DIP14 package
-
50
mA
−50 -
mA
−65 +150 °C
[2] _-
750
mW
SO14 package
[3] _-
500
mW
(T)SSOP14 package
[4] _-
500
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] P_tot derates linearly with 12 mW/K above 70 °C.
[3] P_tot derates linearly with 8 mW/K above 70 °C.
[4] P_tot derates linearly with 5.5 mW/K above 60 °C.
74HC73_4
Product data sheet
Rev. 04 — 19 March 2008
© NXP B.V. 2008. All rights reserved.
4 of 16