DAC1408D650_1011 Datasheet, PDF (88/98 Pages) NXP Semiconductors – Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface

NXP Semiconductors
DAC1408D650
2, 4 or 8 interpolating DAC with JESD204A
Table 199. LN3_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN3_RES1[7:0]
R
-
Description
lane 3 reserved field
Table 200. LN3_CFG_12 register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN3_RES2[7:0]
R
-
Description
lane 3 reserved field
Table 201. LN3_CFG_13 register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN3_FCHK[7:0]
R
-
Description
lane 3 checksum
Table 202. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
2 to 0 PAGE[2:0]
R/W
0h
page_address
DAC1408D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
© NXP B.V. 2010. All rights reserved.
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