DAC1408D650_1011 Datasheet, PDF(68/98 Page) NXP Semiconductors – Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface

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DAC1408D650_1011 Datasheet, PDF (68/98 Pages) NXP Semiconductors – Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface

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10.15.2.9 Page 5 allocation map description

Table 108. Page 5 register allocation map

Address Register name R/W Bit definition

Default[1]

b7

b6

b5

b4

b3

b2

b1

b0

Bin

Hex

0 00h ILA_MON_1_0 R

ILA_MON_LN1[3:0]

ILA_MON_LN0[3:0

uuuuuuuu uuh

1 01h ILA_MON_3_2 R

ILA_MON_LN3[3:0]

ILA_MON_LN2[3:0]

uuuuuuuu uuh

2 02h ILA_BUF_ERR R

-

-

-

-

ILA_BUF_ ILA_BUF_ ILA_BUF_ ILA_BUF_ uuuuuuuu uuh

ERR_LN3 ERR_LN2 ERR_LN1 ERR_LN0

3 03h CA_MON

R

CA_MON_LN3[1:0] CA_MON_LN2[1:0]

CA_MON_LN1[1:0]

CA_MON_LN0[1:0] uuuuuuuu uuh

4 04h DEC_FLAGS R DEC_NIT DEC_NIT DEC_NIT_ DEC_NIT_ DEC_DISP_ DEC_DISP_ DEC_DISP_ DEC_DISP_ uuuuuuuu uuh

_ERR_ _ERR_ ERR_LN1 ERR_LN0 ERR_LN3 ERR_LN2 ERR_LN1 ERR_LN0

LN3

LN2

5 05h KOUT_FLAG R

-

-

-

-

DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ uuuuuuuu uuh

LN3

LN2

LN1

LN0

6 06h K28_LN0_FLAG R

-

-

-

K28_7_LN0 K28_5_LN0 K28_4_LN0 K28_3_LN0 K28_0_LN0 uuuuuuuu uuh

7 07h K28_LN1_FLAG R

-

-

-

K28_7_LN1 K28_5_LN1 K28_4_LN1 K28_3_LN1 K28_0_LN1 uuuuuuuu uuh

8 08h K28_LN2_FLAG R

-

-

-

K28_7_LN2 K28_5_LN2 K28_4_LN2 K28_3_LN2 K28_0_LN2 uuuuuuuu uuh

9 09h K28_LN3_FLAG R

-

-

-

K28_7_LN3 K28_5_LN3 K28_4_LN3 K28_3_LN3 K28_0_LN3 uuuuuuuu uuh

10 0Ah KOUT_

R

-

-

-

UNEXPECTED_

FLAG

-

DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ uuuuuuuu uuh

UNEXP_LN3 UNEXP_LN2 UNEXP_LN1 UNEXP_LN0

11 0Bh LOCK_CNT_ R

MON_LN01

LOCK_CNT_MON_LN1[3:0]

LOCK_CNT_MON_LN0[3:0]

uuuuuuuu uuh

12 0Ch LOCK_CNT_ R

MON_LN23

LOCK_CNT_MON_LN3[3:0]

LOCK_CNT_MON_LN2[3:0]

uuuuuuuu uuh

13 0Dh CS_STATE_LNX R CS_STATE_LN3[1:0] CS_STATE_LN2[1:0]

CS_STATE_LN1[1:0]

CS_STATE_LN0[1:0] uuuuuuuu uuh

14 0Eh RST_BUF_ERR_ R/W RST_

-

-

-

-

-

-

-

00000000 00h

FLAGS

BUF_

ERR_

FLAGS

15 0Fh INTR_MISC_

ENA

R/W INTR_ INTR_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ 00000000 00h

ENA_ ENA_CS_ CS_INIT_ CS_INIT_ BUF_ERR_ BUF_ERR_ BUF_ERR_ BUF_ERR_

CS_ INIT_LN2 LN1

LN0

LN3

LN2

LN1

LN0

INIT_LN3

16 10h FLAG_CNT_LSB R

_LN0

FLAG_CNT_LN0[7:0]

uuuuuuuu uuh

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