DAC1408D650_1011 Datasheet, PDF (18/98 Pages) NXP Semiconductors – Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface

NXP Semiconductors
DAC1408D650
2, 4 or 8 interpolating DAC with JESD204A
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges reach each of the
DACs at different times.
ref clock
TDAC
master clock
PH01
slave 1 clock
PH02
slave 2 clock
PH03
Fig 9. Clock skew case 1: Master is farthest
001aal072
The worst case clock skew is given by t₁ = PH01 – PH03 , where PH0x represents the
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by t = TDAC – t₁ .
DAC1408D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
© NXP B.V. 2010. All rights reserved.
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