PSMN2R0-30YL Datasheet, PDF (8/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
2
a
03aa27
1.5
1
0.5
0
-60
0
60
120 _{Tj (°C)} 180
V_DS
I_D
V_GS(pl)
V_GS(th)
V_GS
Q_GS1 Q_GS2
Q_GS
Q_GD
Q_G(tot)
003aaa508
Fig 14. Gate charge waveform definitions
Fig 13. Normalized drain-source on-state
resistance factor as a function of junction
temperature
10
V_GS
(V)
8
V_DS = 12 (V)
6
003aac473
V_DS = 19 (V)
4
2
0
0
20
40
60
80
Q_G (nC)
5000
C
C_iss
(pF)
4000
3000
C_oss
2000
1000
C_rss
0
10^-1
1
003aac478
10 _{VDS (V)} 10²
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer
capacitances as a function of drain-source
voltage; typical values
PSMN2R0-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
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