PSMN2R0-30YL Datasheet, PDF (7/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
8000
C
(pF)
6000
4000
C_iss
C_rss
003aac480
2000
0
0
2
4
6
8
10
V_GS (V)
3
V_GS(th)
(V)
2
1.5
1
0.5
0
-60
max
typ
min
003aab272
0
60
120
180
T_j (°C)
Fig 9. Input and reverse transfer capacitances as
a function of gate-source voltage; typical
values
Fig 10. Gate-source threshold voltage as a
function of junction temperature
10^−3
I_D
(A)
10^−4
003aab271
min typ
max
4
R_DSon
(mΩ)
3.5
3
003aac476
2.5
10^−5
2
10^−6
0
0.5
1
1.5
2
2.5
V_GS (V)
1.5
2
4
6
8 _{VGS (V)} 10
Fig 11. Sub-threshold drain current as a function
of gate-source voltage
Fig 12. Drain-source on-state resistance as a
function of gate-source voltage; typical
values
PSMN2R0-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
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