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PSMN2R0-30YL Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET | |||
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PSMN2R0-30YL
N-channel TrenchMOS logic level FET
Rev. 01 â 10 September 2008
Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
 High efficiency due to low switching
and conduction losses
 Suitable for logic level gate drive
sources
1.3 Applications
 Class-D amplifiers
 DC-to-DC converters
 Motor control
 Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS
drain-source voltage Tj ⥠25 °C; Tj ⤠150 °C
-
-
30 V
ID
drain current
Tmb = 25 °C; VGS = 10 V; [1] -
-
100 A
see Figure 1; see Figure 3;
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
97 W
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
-
7.5 -
nC
Static characteristics
RDSon
drain-source
VGS = 10 V; ID = 15 A;
on-state resistance Tj = 25 °C; see Figure 12
-
1.56 2
mâ¦
[1] Continuous current is limited by package.
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