BUK135-50L Datasheet, PDF (8/13 Pages) NXP Semiconductors – Logic level TOPFET

Philips Semiconductors
Logic level TOPFET
SMD version of BUK124-50L
Product Specification
BUK135-50L
I_IS & I_ISL
10E-3
1E-3
BUK135-50L
I_ISL
00E-6
I_IS
10E-6
-50
0
50
100
150
T_j / ^OC
Fig.14. Typical DC input currents. I_IS & I_ISL = f(T_j);
normal & latched; conditions: V_IS = 5 V; V_PS = 5 V
V_IS(TO) / V
3.0
BUK135-50L
2.5
2.0
max .
1.5
typ.
1.0
min.
0.5
0.0
-50
0
50
100
150
T_j / ^OC
Fig.15. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
10 ^{IIS / mA}
BUK135-50L
8
6
4
2
0
0
2
V_IS⁴/ V
6
8
Fig.16. Typical input clamping characteristic.
I_I = f(V_IS); normal operation, T_j = 25˚C
I_DSP / mA
2.5
BUK135-50L
2.0
1.5
1.0
I_DSP is constant from Vds = 2V to 40V
0.5
0
0
1
2
3
4
5
V_DS / V
Fig.17. Off state drain current characteristic.
I_DSP = f(V_DS); conditions: T_j = 25˚C; V_PS = 5 V; V_IS = 0 V
I_DSP / mA
2.5
BUK135-50L
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
6
7
8
V_PS / V
Fig.18. Off state drain current vs protection supply.
I_DSP = f(V_PS); T_j = 25˚C; V_DS = 13 V; V_IS = 0 V
I_DSP / mA
2.5
BUK135-50L
2.0
1.5
-50
0
50
100
150
T_j / ^OC
Fig.19. Typical off state drain current I_DSP = f(T_j);
conditions: V_DS = 13 V; V_PS = 5 V; V_IS = 0 V
July 2002
8
Rev 1.100