BUK135-50L Datasheet, PDF (6/13 Pages) NXP Semiconductors – Logic level TOPFET

Philips Semiconductors
Logic level TOPFET
SMD version of BUK124-50L
CAPACITANCES
T_mb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER
C_iss
Input capacitance
C_oss
Output capacitance
C_rss
Reverse transfer capacitance
C_pso
Protection supply pin
capacitance
C_fso
Flag pin capacitance
CONDITIONS
V_DS = 25 V; V_IS = 0 V
V_DS = 25 V; V_IS = 0 V
V_DS = 25 V; V_IS = 0 V
V_PS = 5 V
V_FS = 5 V; V_PS = 0 V
Product Specification
BUK135-50L
MIN.
-
-
-
-
TYP.
710
370
26
22
MAX.
1050
550
40
-
UNIT
pF
pF
pF
pF
-
12
-
pF
P_D%
120
Normalise Power Derating
100
80
60
40
20
0
0
20
40
60
80
100 120 140
T_mb / ^OC
Fig.4. Normalised limiting power dissipation.
P_D% = 100⋅P_D/P_D(25˚C) = f(T_mb)
I_D / A
40
BUK135-50L
30
20
10
0
0
20
40
60
80
100 120 140
T_mb / ^OC
Fig.5. Continuous drain current.
I_D = f(T_amb); condition: V_IS = 5 V
I_D / A
80
BUK135-50L
70
V_IS / V =
60
7
6
50
5
40
4
30
20
3
10
0
0
2
4
6
8
10
12
14
16
V_DS / V
Fig.6. Typical output characteristics, T_j = 25˚C.
I_D = f(V_DS); parameter V_IS; t_p = 300 µs & t_p < t_{d sc}
80 ^{ID / A}
y
BUK135-50L
70
V_IS / V =
7
60
6
50
5
40
4
30
20
3
10
0
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
V_DS / V
2
2 2.2
Fig.7. Typical on-state characteristics, T_j = 25˚C.
I_D = f(V_DS); parameter V_IS; t_p = 300 µs
July 2002
6
Rev 1.100