PN512_11 Datasheet, PDF (79/125 Pages) NXP Semiconductors – Transmission module Integrated data mode detector

NXP Semiconductors
PN512
Transmission module
11.2 Separated Read/Write strobe
non multiplexed
address
low
low
low
high
high
high
ADDRESS
DECODER
multiplexed address/data AD0...AD7)
address latch enable (ALE)
not read strobe (NRD)
not write (NWR)
PN512
NCS
A5*
A4*
A3
A2
A1
A0
D0...D7
ALE
NRD
NWR
address bus
ADDRESS
DECODER
PN512
NCS
address bus (A0...A3[A5*])
data bus (D0...D7)
high
not data strobe (NRD)
not write (NWR)
A0...A3[A5*]
D0...D7
ALE
NRD
NWR
remark: *depending on the package type.
Fig 25. Connection to host controller with separated Read/Write strobes
001aan223
For timing requirements refer to Section 25.2 “8-bit parallel interface timing”.
11.3 Common Read/Write strobe
non multiplexed
address
low
low
low
high
high
low
ADDRESS
DECODER
multiplexed address/data AD0...AD7)
address strobe (AS)
not data strobe (NDS)
read not write (RD/NWR)
PN512
NCS
A5*
A4*
A3
A2
A1
A0
D0...D7
ALE
NRD
NWR
address bus
ADDRESS
DECODER
PN512
NCS
address bus (A0...A3[A5*])
Data bus (D0...D7)
high
not data strobe (NDS)
read not write (RD/NWR)
A0...A3[A5*]
D0...D7
ALE
NRD
NWR
remark: *depending on the package type.
Fig 26. Connection to host controller with common Read/Write strobes
001aan224
For timing requirements refer to Section 25.2 “8-bit parallel interface timing”
PN512
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 18 May 2011
111337
© NXP B.V. 2011. All rights reserved.
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