PN512_11 Datasheet, PDF (6/125 Pages) NXP Semiconductors – Transmission module Integrated data mode detector

NXP Semiconductors
PN512
Transmission module
SDA/NSS/RX EA I2C
24
32 1
D6/ADR_0/
D2/ADR_4 D4/ADR_2 MOSI/MX
D5/ADR_1/ D7/SCL/
D1/ADR_5 D3/ADR_3 SCK/DTRQ MISO/TX
PVDD PVSS
25 26 27 28 29 30 31
2
5
SPI, UART, I²C-BUS INTERFACE CONTROL
FIFO CONTROL
64-BYTE FIFO
BUFFER
CONTROL REGISTER
BANK
STATE MACHINE
COMMAND REGISTER
PROGRAMABLE TIMER
INTERRUPT CONTROL
VOLTAGE
MONITOR
AND
POWER ON
DETECT
3
DVDD
4
DVSS
15
AVDD
18 _AVSS
RESET
CONTROL
POWER-DOWN
CONTROL
6 _NRSTPD
23
IRQ
MIFARE CLASSIC UNIT
CRC16
GENERATION AND CHECK
RANDOM NUMBER
GENERATOR
AMPLITUDE
RATING
REFERENCE
VOLTAGE
ANALOG TEST
MULTIPLEXOR
AND
DIGITAL TO
ANALOG
CONVERTER
PARALLEL/SERIAL
CONVERTER
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING
BIT ENCODING
SERIAL DATA SWITCH
ANALOG TO DIGITAL
CONVERTER
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
OSCILLATOR
7
MFIN
8 _MFOUT
9 _SVDD
21
OSCIN
22 _OSCOUT
I-CHANNEL
AMPLIFIER
I-CHANNEL
DEMODULATOR
Q-CHANNEL
AMPLIFIER
Q-CHANNEL
DEMODULATOR
Q-CLOCK
GENERATION
TEMPERATURE
SENSOR
TRANSMITTER CONTROL
16 19 20
17
VMID AUX1 AUX2
RX
Fig 2. Detailed block diagram of the PN512
10, 14 11
TVSS TX1
13
12
TX2 TVDD
001aak602
PN512
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 18 May 2011
111337
© NXP B.V. 2011. All rights reserved.
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