PN512_11 Datasheet, PDF (29/125 Pages) NXP Semiconductors – Transmission module Integrated data mode detector

NXP Semiconductors
PN512
Transmission module
9.2.1.12 WaterLevelReg
Defines the level for FIFO under- and overflow warning.
Table 38. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b
7
6
5
4
3
2
1
0
0
0
WaterLevel
Access RFU
RFU
r/w
r/w
r/w
r/w
r/w
r/w
Rights
Table 39. Description of WaterLevelReg bits
Bit
Symbol
Description
7 to 6 -
Reserved for future use.
5 to 0
WaterLevel
This register defines a warning level to indicate a FIFO-buffer over- or
underflow:
The bit HiAlert in Status1Reg is set to logic 1, if the remaining number
of bytes in the FIFO-buffer space is equal or less than the defined
number of WaterLevel bytes.
The bit LoAlert in Status1Reg is set to logic 1, if equal or less than
WaterLevel bytes are in the FIFO.
Note: For the calculation of HiAlert and LoAlert see Table 30
9.2.1.13 ControlReg
Miscellaneous control bits.
Table 40. ControlReg register (address 0Ch); reset value: 00h, 00000000b
7
6
5
4
3
2
1
0
TStopNow TStartNow WrNFCIDtoFIFO Initiator 0
RxLastBits
Access
w
w
Rights
dy
r/w RFU r
r
r
Table 41. Description of ControlReg bits
Bit Symbol
Description
7
TStopNow
Set to logic 1, the timer stops immediately.
Reading this bit will always return 0.
6
TStartNow
Set to logic 1 starts the timer immediately.
Reading this bit will always return 0.
5
WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the
FIFO.
Afterwards the bit is cleared automatically
4
Initiator
Set to logic 1, the PN512 acts as initiator, otherwise it acts as target
3
-
Reserved for future use.
2 to 0 RxLastBits
Shows the number of valid bits in the last received byte. If zero, the
whole byte is valid.
PN512
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 18 May 2011
111337
© NXP B.V. 2011. All rights reserved.
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