SC28L201 Datasheet, PDF (74/110 Pages) NXP Semiconductors – 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
8.6 Registers of the I/O ports
8.6.1 Input Port Change Register Lower Nibble, A (IPCRL)
This register may be read to determine the current logical level of the I/O pins and
examine the output of the change detectors assigned to each pin. If the change detection
is not enabled or if the pin is configured as an output, the associated change field will read
‘0’.
Table 61: IPCRL - Input Port Change Register Lower Nibble, A (address 0x14)
bit description
Bit Symbol Description
7
∆I/O3A change.
0 = no change
1 = change
6
∆I/O2A change.
0 = no change
1 = change
5
∆I/O1A change.
0 = no change
1 = change
4
∆I/O0A change.
0 = no change
1 = change
3
I/O3A state. Reads the actual logic level at the pin.
1 = HIGH level
0 = LOW level
2
I/O2A state. Reads the actual logic level at the pin.
1 = HIGH level
0 = LOW level
1
I/O1A state. Reads the actual logic level at the pin.
1 = HIGH level
0 = LOW level
0
I/O0A state. Reads the actual logic level at the pin.
1 = HIGH level
0 = LOW level
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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