SC28L201 Datasheet, PDF (38/110 Pages) NXP Semiconductors – 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Table 5: GCCR - Global Configuration Control Register (address 0x66) bit description
Bit Symbol Description
2:1 IVC
Interrupt Vector Control
00 = no interrupt vector
01 = IVR[7:0]
10 = IVR[7:1] + channel code
11 = IVR[7:5] + interrupt type + channel code
The IVC field controls if and how the assertion of IACKN (the interrupt
acknowledge pin) will form the interrupt vector for the UART. If 00, no vector will
be presented during an IACKN cycle. The bus will be driven HIGH (0xFF). If the
field contains a 01, the contents of the IVR, Interrupt Vector Register, will be
presented as the interrupt vector without modification.
If IVC = 10, the channel code will replace the LSB of the IVR; if IVC = 11 then a
modified interrupt type and channel code replace the 3 LSBs of the IVR.
Remark: The modified type field IVR[2:1] is:
10: Receiver without error
11: Receiver with error
01: Transmitter
00: all remaining sources
0
Interrupt status masking
0 = ISR unmasked
1 = ISR read masked by IMR
This bit controls the readout mode of the Interrupt Status Register, ISR. If set,
the ISR reads the current status masked by the IMR, that is, only interrupt
sources enabled in the IMR can ever show a ‘1’ in the ISR. If cleared, the ISR
shows the current status of the interrupt source without regard to the Interrupt
Mask setting.
Table 6: DACKN assertion time
X1/SCLK
Number of SCLK cycles
3.6864 MHz
7.3728 MHz
14.7456 MHz
29.4912 MHz
1_{⁄2 to 1}
1_{⁄2 to 1}
1_{⁄2 to 1}
1 to 2
33.1776 MHz
2 to 3
44.2368 MHz
2 to 3
Delay
136 ns to 272 ns
68 ns to 136 ns
34 ns to 68 ns
34 ns to 68 ns
60 ns to 90 ns
46 ns to 68 ns
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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