SC28L201 Datasheet, PDF (18/110 Pages) NXP Semiconductors – 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
When legacy code is called using the lower 16 address portions (0x00 to 0x0F), the I/O
pins will be switched to input. Legacy code would expect to see the I/OA pins to be input
and the I/OB pins to be output driving HIGH as a default condition. In calling legacy code,
this condition must be accounted for.
7.4 UART operation
7.4.1 Receiver and transmitter
The Dual UART has two full duplex asynchronous receiver/transmitters. The operating
frequency for the receiver and transmitter can be selected independently from the baud
rate generator, the counter, or from an external input. Registers that are central to basic
full-duplex operation are the mode registers (MR0, MR1 and MR2), the clock select
registers (RxCSR and TxCSR), the command register (CR), the status register (SR), the
transmit holding register (TxFIFO), the receive holding register (RxFIFO), interrupt status
register (ISR) and interrupt mask register (IMR). MR3 controls the automatic activity or the
Xon/Xoff flow control, Address recognition, multi-drop (‘9-bit’ mode) and general purpose
character recognition. Because MR3 does not exist in legacy UARTs, these features
should be disabled before legacy code is loaded.
7.4.2 Transmitter status bits
The SR (Status Register) contains two bits that show the condition of the transmitter FIFO.
These bits are TxRDY and Tx Idle. TxRDY means the TxFIFO has space available for one
or more bytes; Tx Idle means the TxFIFO is completely empty and the last stop bit has
been completed: the transmitter is underrun. Tx Idle can not be active without TxRDY also
being active. These two bits will go active upon initial enabling of the transmitter.
The transmitter status bits are normally cleared by servicing the interrupt condition they
represent or by Tx reset or Tx disable commands.
Transmission resumes and the Tx Idle bit is cleared when the CPU loads at least one new
character into the TxFIFO. The TxRDY will not extinguish until the TxFIFO is completely
full. The TxRDY bit will always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by a hardware reset, a transmitter reset in the command
register or by the transmitter disable bit also in the command register (CR). The
transmitter must be explicitly enabled via the CR before transmission can begin. Note that
characters cannot be loaded into the TxFIFO while the transmitter is disabled, hence it is
necessary to enable the transmitter and then load the TxFIFO. It is not possible to load the
TxFIFO and then enable the transmission.
Note the difference between transmitter disable and transmitter reset.
Either hardware or software may cause the reset action. When reset the transmitter stops
transmission immediately. The transmit data output will be driven HIGH, transmitter status
bits set to zero and any data remaining in the TxFIFO is effectively discarded.
The transmitter disable is controlled by the Tx Enable bit in the command register. Setting
this bit to zero will not stop the transmitter immediately but will allow it to complete any
tasks presently underway. It is only when the last character in the TxFIFO and its stop
bit(s) have been transmitted that the transmitter will go to its disabled state. While the
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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