SC28L201 Datasheet, PDF (15/110 Pages) NXP Semiconductors – 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
7.2 Timing circuits
7.2.1 Crystal oscillator
The crystal oscillator operates directly from a crystal, tuned between 7.0 MHz and
16.2 MHz connected across the X1/SCLK and X2 inputs with a minimum of external
components. BRG values listed for the clock select registers correspond to a
14.7456 MHz crystal frequency. Use of different frequencies will change the ‘standard’
baud rates by precisely the ratio of 14.7456 MHz to the different crystal frequency.
An external clock up to 50 MHz frequency range may be connected to X1/SCLK pin. If an
external clock is used instead of a crystal, X1/SCLK must be driven and X2 left floating or
driving a load of not more than 2 CMOS or TTL equivalents. The X1/SCLK clock serves as
the basic timing reference for the baud rate generator (BRG) and is available to the
programmable BRG (PBRG), counter-timers, control logic and the UART receivers and
transmitters.
7.2.2 Baud rage generator (BRG)
The baud rate generator operates from the oscillator or external X1/SCLK clock input and
generates 27 commonly-used data communications baud rates (including MIDI) ranging
from 50 baud to 921.6 kBd. These common rates may be increased (up to 3.125 MBd)
when faster clocks are used on the X1/SCLK clock input. (See Section 8.2.5 “Receiver
Clock Select Register (RxCSR) and Transmitter Clock Select Register (TxCSR)”.) All of
these are available simultaneously for use by any receiver or transmitter. The clock
outputs from the BRG are at 16× (the actual baud rate).
Please see Section 7.2.3 “Counter/Timer” for a description of the frequency error that the
asynchronous protocol may tolerate. Depending on character length it varies from 4.1 %
to 6.7 %.
7.2.3 Counter/Timer
The two Counter/Timers are programmable 16-bit dividers that are used for generating
miscellaneous clocks or generating time-out periods or counting characters received by
the receivers. Interrupts may be generated any time the counter passes through 0x00.
The counter/timer clocks may be used simultaneously by receiver, transmitter, I/O pin,
time-out logic, or interrupt.
7.2.3.1 Counter/Timer programming
The Counter/Timer is a 16-bit programmable divider that operates in one of four modes:
character count, counter, timer, and time-out. Character count counts characters. The
Timer mode generates a square wave or a pulse. If a square wave is programmed, the
counter counts down once for the HIGH portion, and once for the LOW portion of the
square wave. In the Pulse mode it counts down and outputs a pulse one-clock cycle.
Recall that the input to the counter may be from many places other than the X1 crystal
clock.
In the Counter mode it generates a time delay. In this mode, the counter effectively stops
at the end of the time-out, it does not continue until another START/STOP timer command
sequence is given. In the Time-out mode, it monitors the time between received
characters. If the time between any two characters is longer than the programmed time,
and interrupt is generated. This activity is similar to a receiver watchdog timer, but the true
meaning is that the data has stopped. The watchdog action indicates there is data in the
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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