SC28L201 Datasheet, PDF (28/110 Pages) NXP Semiconductors – 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
updated by an arbitration or bidding unit that selects the highest value presented by the
various interrupt sources that may be enabled at any time. The values used are under the
control of the software and the FIFO fill counters.
The arbitration is exercised over the several systems within the UART that may generate
an interrupt. These will be referred to as ‘interrupt sources’. There are 11 in all and may of
those have several sublevels. In general the arbitration is based on the fill level of the
receiver FIFO or the empty level of the transmitter FIFO. The FIFO levels are encoded into
an 8-bit number, which is concatenated to the channel number and source identification
code. All of this is compared (via the bidding or arbitration process) to a user defined
‘threshold’. Whenever a source exceeds the numerical value of the threshold the interrupt
will be generated.
Interrupt sources that do not have a FIFO are each provided with a ‘programmable field’
that will determine their importance in the arbitration and type identification process. (See
Table 4.)
At the time of interrupt acknowledge (IACKN) the source which has the highest bid (not
necessarily the source that caused the interrupt to be generated) will be captured in a
Current Interrupt Register (CIR). This register will contain the complete definition of the
interrupting source: channel, types of interrupt (receiver, transmitter, change-of-state, and
so on) and FIFO fill level. The value of the bits in the CIR are used to drive the interrupt
vector and global registers such that controlling processor may be steered directly to the
proper service routine. A single read operation to the CIR provides all the information
needed to qualify and quantify the most common interrupt sources.
Using IACKN automatically provides an update of the CIR and presents that data as an
interrupt vector or an interrupt vector modified. Without the use of the IACKN, and update
CIR command will be issued followed by a read of the CIR.
The interrupt sources are:
• Receiver without error
• Receiver with error for each channel
• Receiver Watchdog Time-out Event
• Transmitter
• Change in break received status per channel
• Rx loopback error
• Change of state on channel input pins
• Xon/Xoff character recognition
• Counter/Timer
• Address character recognition
• No interrupt active (very useful in polled service and as a test value to terminate
interrupt service) when CIR = 0x00
Transmit FIFO empty level and Receiver FIFO fill levels are unique for each channel and
may be set at any level.
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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