ISP1506A_08 Datasheet, PDF (63/80 Pages) NXP Semiconductors – ULPI Hi-Speed USB OTG transceiver

NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
Table 56. Dynamic characteristics: analog I/O pins (DP and DM) …continued
V_CC = 3.0 V to 3.6 V; V_CC(I/O) = 1.65 V to 1.95 V; T_amb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
t_PHZ
driver disable delay from TX_ENABLE to DP, DM;
HIGH level
see Figure 28
-
-
12
ns
t_PLZ
driver disable delay from TX_ENABLE to DP, DM;
LOW level
see Figure 28
-
-
12
ns
t_PZH
driver enable delay to
TX_ENABLE to DP, DM;
HIGH level
see Figure 28
-
-
20
ns
t_PZL
driver enable delay to
TX_ENABLE to DP, DM;
LOW level
see Figure 28
-
-
20
ns
Receiver timing
Differential receiver
t_PLH(rcv) receiver propagation
delay (LOW to HIGH)
DP, DM to DAT, SE0;
see Figure 29
-
-
17
ns
t_PHL(rcv) receiver propagation
delay (HIGH to LOW)
DP, DM to DAT, SE0;
see Figure 29
-
-
17
ns
V_OH
t_HSR, t_FR, t_LR
90 %
t_HSF, t_FF, t_LF
90 %
10 %
V_OL
Fig 26. Rise time and fall time
10 %
004aaa861
1.8 V
logic input 0.9 V
0V
V_OH
differential
data lines
V_OL
t_PLH(drv)
V_CRS
0.9 V
t_PHL(drv)
V_CRS
004aaa573
Fig 27. Timing of DAT and SE0 when transmitting to
DP and DM
1.8 V
logic _{0.9 V}
input
0V
V_OH
differential
data lines
V_OL
t_PZH
t_PZL
V_CRS
0.9 V
t_PHZ
t_PLZ
V_OH − 0.3 V
V_OL + 0.3 V
004aaa574
Fig 28. Timing of TX_ENABLE to DP and DM
2.0 V
differential
data lines
0.8 V
V_OH
V_CRS
t_PLH(rcv)
logic output
0.9 V
V_OL
V_CRS
t_PHL(rcv)
0.9 V
004aaa985
Fig 29. Timing of DAT and SE0 when receiving from
DP and DM
15.1 ULPI timing
ULPI interface timing requirements are given in Figure 30. This timing applies to
synchronous mode only. All timing is measured with respect to the ISP1506 CLOCK pin.
All signals are clocked on the rising edge of CLOCK.
ISP1506A_ISP1506B_2
Product data sheet
Rev. 02 — 28 August 2008
© NXP B.V. 2008. All rights reserved.
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