ISP1506A_08 Datasheet, PDF (22/80 Pages) NXP Semiconductors – ULPI Hi-Speed USB OTG transceiver

NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
completed. After every reset, an RXCMD is sent to the link to update USB status
information. After this sequence, the ULPI bus is ready for use and the link can start USB
operations.
When the internal PLL is stable, the ISP1506 will drive a 60 MHz clock out from the
CLOCK pin when DIR deasserts. An example start-up sequence is shown in Figure 6.
The recommended power-up sequence for the link is as follows:
1. The link waits for 1 ms, ignoring all the ULPI pin status.
2. The link may start to detect DIR status level. If DIR is detected as LOW for three clock
cycles, the link may send a RESET command.
The ULPI interface is ready for use.
ISP1506A_ISP1506B_2
Product data sheet
Rev. 02 — 28 August 2008
© NXP B.V. 2008. All rights reserved.
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