ISP1506A_08 Datasheet, PDF (35/80 Pages) NXP Semiconductors – ULPI Hi-Speed USB OTG transceiver

NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
DP or
DM
DATA EOP
CLOCK
USB interpacket delay (8 to 192 high-speed bit times)
IDLE
SYNC
DATA
[3:0]
D_N−4
D_N−2
D_N
D_N−3
D_N−1
turnaround
DIR
STP
TXCMD D0 D1
NXT
RX end delay
(three to eight clocks)
link decision time (1 to 14 clocks)
Fig 14. High-speed receive-to-transmit packet timing
TX start delay
(one to two clocks)
004aaa892
9.9 Preamble
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
ISP1506 operates just as in full-speed mode, and sends all data with the full-speed rise
time and fall time. Whenever the link transmits a USB packet in preamble mode, the
ISP1506 will automatically send a preamble header at full-speed bit rate before sending
the link packet at low-speed bit rate. The ISP1506 will ensure a minimum gap of four
full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the
low-speed packet SYNC. The ISP1506 will drive a J for at least one full-speed bit time
after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.
An example transmit packet is shown in Figure 15.
In preamble mode, the ISP1506 can also receive low-speed packets from the full-speed
bus.
ISP1506A_ISP1506B_2
Product data sheet
Rev. 02 — 28 August 2008
© NXP B.V. 2008. All rights reserved.
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