ISP1506A_08 Datasheet, PDF (44/80 Pages) NXP Semiconductors – ULPI Hi-Speed USB OTG transceiver

NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
DATA0
(TX_ENABLE)
DATA1
(DAT)
DATA2
(SE0)
DP
SYNC
TRANSMIT
DATA
EOP
RECEIVE
SYNC
DATA
EOP
DM
Fig 20. Example of transmit followed by receive in 3-pin serial mode
004aaa982
9.14 Aborting transfers
The ISP1506 supports aborting transfers on the ULPI bus. For details, refer to Ref. 3
“UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1”, Section 3.8.4.
9.15 Avoiding contention on the ULPI data bus
Because the ULPI data bus is bidirectional, avoid situations in which both the link and the
PHY simultaneously drive the data bus.
The following points must be considered while implementing the data bus drive control on
the link.
After power-up and clock stabilization, default states are as follows:
• The ISP1506 drives DIR to LOW.
• The data bus is input to the ISP1506.
• The ULPI link data bus is output, with all data bus lines driven to LOW.
When the ISP1506 wants to take control of the data bus to initiate a data transfer, it
changes the DIR value from LOW to HIGH.
At this point, the link must disable its output buffers. This must be as fast as possible so
the link must use a combinational path from DIR.
The ISP1506 will not immediately enable its output buffers, but will delay the enabling of
its buffers until the next clock edge, avoiding bus contention.
When the data transfer is no longer required by the ISP1506, it changes DIR from HIGH to
LOW and starts to immediately turn off its output drivers. The link senses the change of
DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,
avoiding data bus contention.
ISP1506A_ISP1506B_2
Product data sheet
Rev. 02 — 28 August 2008
© NXP B.V. 2008. All rights reserved.
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