ISP1506A_08 Datasheet, PDF (61/80 Pages) NXP Semiconductors – ULPI Hi-Speed USB OTG transceiver

NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
15. Dynamic characteristics
Table 54. Dynamic characteristics: reset and clock
V_CC = 3.0 V to 3.6 V; V_CC(I/O) = 1.65 V to 1.95 V; T_amb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at V_CC = 3.3 V; V_CC(I/O) = 1.8 V; T_amb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Reset
t_W(POR)
internal power-on reset pulse
width
0.2
-
t_{w(REG1V8_H)}
REG1V8 HIGH pulse width
2
-
t_{w(REG1V8_L)}
REG1V8 LOW pulse width
11
-
t_{W(RESET_N)}
external RESET_N pulse width
200
-
t_PWRUP
regulator start-up time
4.7 µF ± 20 % capacitor
-
-
each on pins REG1V8
and REG3V3
Crystal or clock applied to XTAL1
f_i(XTAL1)
input frequency on pin XTAL1
ISP1506ABS
ISP1506BBS
-
19.2
-
26
t_{jit(i)(XTAL1)RMS}
RMS input jitter on pin XTAL1
ISP1506ABS
ISP1506BBS
-
-
-
-
δ_i(XTAL1)
input duty cycle on pin XTAL1 applicable only when
[1] _-
50
clock is applied on
pin XTAL1
∆f_i(XTAL1)
input frequency tolerance on
pin XTAL1
-
50
t_r(XTAL1)
rise time on pin XTAL1
only for square wave
-
-
input
t_f(XTAL1)
fall time on pin XTAL1
only for square wave
-
-
input
V_(XTAL1)(p-p)
peak-to-peak voltage on
pin XTAL1
only for square wave
input
0.566 -
Output CLOCK characteristics
f_o(CLOCK)
t_{jit(o)(CLOCK)RMS}
δ_o(CLOCK)
output frequency on pin CLOCK
RMS output jitter on pin CLOCK
output clock duty cycle on
pin CLOCK
-
60
-
-
45
50
t_startup(PLL)
PLL start-up time
t_{startup(o)(CLOCK)} output CLOCK start-up time
measured from power
good or assertion of
pin STP
-
650
450
650
Max
-
-
-
-
1
-
-
200
300
-
200
5
5
1.95
-
500
55
-
900
[1] The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.
Unit
µs
µs
µs
ns
ms
MHz
MHz
ps
ps
%
ppm
ns
ns
V
MHz
ps
%
µs
µs
ISP1506A_ISP1506B_2
Product data sheet
Rev. 02 — 28 August 2008
© NXP B.V. 2008. All rights reserved.
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