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PSMN3R4-30PL Datasheet, PDF (6/15 Pages) NXP Semiconductors – N-channel 30 V 3.4 m logic level MOSFET
NXP Semiconductors
PSMN3R4-30PL
N-channel 30 V 3.4 mΩ logic level MOSFET
6. Characteristics
Table 6. Characteristics
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Min
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.3
see Figure 10; see Figure 11
ID = 1 mA; VDS = VGS; Tj = 175 °C;
0.5
see Figure 11
ID = 1 mA; VDS = VGS; Tj = -55 °C;
-
see Figure 11
IDSS
IGSS
RDSon
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
VDS = 30 V; VGS = 0 V; Tj = 125 °C
-
gate leakage current
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
drain-source on-state resistance VGS = 10 V; ID = 10 A; Tj = 175 °C;
-
see Figure 12
VGS = 4.5 V; ID = 10 A; Tj = 25 °C;
-
see Figure 13
VGS = 10 V; ID = 10 A; Tj = 100 °C;
-
see Figure 12
VGS = 4.5 V; ID = 10 A; Tj = 175 °C;
-
see Figure 12
VGS = 10 V; ID = 10 A; Tj = 25 °C;
see Figure 13
[1] -
RG
gate resistance
f = 1 MHz
-
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 15 V; VGS = 10 V;
-
see Figure 14; see Figure 15
QGS
QGS(th)
gate-source charge
pre-threshold gate-source
charge
ID = 0 A; VDS = 0 V; VGS = 10 V
-
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
-
see Figure 14; see Figure 15
-
-
QGS(th-pl)
post-threshold gate-source
-
charge
QGD
gate-drain charge
-
VGS(pl)
gate-source plateau voltage
VDS = 15 V; see Figure 14;
-
see Figure 15
Ciss
input capacitance
Coss
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
-
Tj = 25 °C; see Figure 16
-
Crss
reverse transfer capacitance
-
Typ Max Unit
-
-
V
-
-
V
1.7 2.15 V
-
-
V
-
2.45 V
0.3 5
µA
-
100 µA
10
100 nA
10
100 nA
-
6.46 mΩ
3.5 4.1 mΩ
-
6.1 mΩ
-
7.79 mΩ
2.8 3.4 mΩ
1
-
Ω
64
-
nC
58
-
nC
31
-
nC
12
-
nC
6.2 -
nC
5.8 -
nC
8
-
nC
2.8 -
V
3907 -
pF
822 -
pF
356 -
pF
PSMN3R4-30PL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 2 November 2010
© NXP B.V. 2010. All rights reserved.
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