PSMN1R5-25YL Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN1R5-25YL
N-channel TrenchMOS logic level FET
Table 6. Characteristics …continued
Symbol Parameter
Conditions
Source-drain diode
V_SD
source-drain voltage I_S = 25 A; V_GS = 0 V; T_j = 25 °C;
see Figure 17
t_rr
reverse recovery time I_S = 20 A; dI_S/dt = -100 A/µs; V_GS = 0 V;
Q_r
recovered charge
V_DS = 20 V
[1] Tested to JEDEC standards where applicable.
Min Typ Max Unit
-
0.78 1.2 V
-
43
-
ns
-
50
-
nC
80
I_D
(A)
60
40
20
0
0
003aac903
T_j = 150 ˚C
25 ˚C
1
2
3 _{VGS (V)} 4
180
I_D
(A)
10 ₄
3.6
150 _3.4
3.2
120
003aac902
3
90
2.8
60
2.6
30
V_GS (V) = 2.4
0
0
2
4
6
8
10
V_DS (V)
Fig 5. Transfer characteristics: drain current as a
Fig 6. Output characteristics: drain current as a
function of gate-source voltage; typical values
function of drain-source voltage; typical values
180
g_fs
(S)
150
120
90
003aac909
4
R_DSon
(mΩ)
3
2
003aac910
V_GS (V) = 3.4
4
60
10
1
30
0
0
20
40 _{ID (A)} 60
0
0
50
100 _{ID (A)} 150
Fig 7. Forward transconductance as a function of
drain current; typical values
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
PSMN1R5-25YL_1
Product data sheet
Rev. 01 — 16 June 2009
© NXP B.V. 2009. All rights reserved.
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